1. Field of the Invention
The present invention generally relates to generating data strobe signals, and more particularly to generating data strobe signals for high speed dynamic random access memories (DRAMs).
2. Description of the Related Art
DRAMs are designed to change output data at a maximum speed of one output data per clock cycle. However, Double Data Rate (DDR) synchronous DRAMs (SDRAMs) can change output data at double that rate. Illustratively, at a rising edge of the clock, a DDR SDRAM can output a first data, and at the next falling edge of the clock, the DDR SDRAM can output a second data, and at the next rising edge of the clock, the DDR SDRAM can output a third data, and so on.
When a DDR SDRAM outputs new data, it also asserts a data strobe signal called a DQS signal. The DQS signal is aligned with the output data of the DDR SDRAM. Typically, the DDR SDRAM is coupled to an SDRAM interface which receives data and the DQS signal from the DDR SDRAM. The SDRAM interface may use the DQS signal from the DDR SDRAM as a clock signal that, when asserted, will trigger a data latch in the SDRAM interface to strobe data from the DDR SDRAM into the data latch. However, because it takes time for the data from the DDR SDRAM to stabilize at the input of the data latch, the DQS signal being asserted at the data latch does not guarantee that valid data are present at the input of the data latch in the SDRAM interface. Therefore, the DQS signal needs to be delayed by making the DQS signal go through a delay circuit so that when the data latch is triggered by the delayed asserted DQS signal, the data at the input of the data latch is stable and valid. If the delay circuit delays the asserted DQS signal too much, the data latch could capture invalid data or even data of the next memory cycle. If the delay circuit delays the asserted DQS signal too little, the data latch could capture invalid data or even data of the previous memory cycle. The goal is that when the asserted DQS signal reaches the data latch, the data from the DDR SDRAM at the input of the data latch is stable and valid. This goal may be achieved by ensuring that if the data from the DDR SDRAM starts to appear at the input of the data latch on a clock edge at time t1 and the next clock edge is at time t2, the delay circuit should cause the delayed asserted DQS signal to arrive at the data latch at approximately ½(t1+t2). On a timing diagram, this point of time is called the center of the data eye.
FIG. 1 shows a timing diagram of the clock signal, the DQS signal at the output of the DDR SDRAM, the data output of the DDR SDRAM at its own output, the delayed DQS signal at the input of the data latch, and the data output of the DDR SDRAM at the input of the data latch. The clock signal, the DQS signal, and the delayed DQS signal each have the same period. At a rising edge of the clock signal at time T1, the DDR SDRAM asserts a HIGH DQS signal and generates data output 10a. At time T2, the data output 10a reaches the data latch as data output 10b. The asserted HIGH DQS signal, after propagating through the delay circuit, reaches the data latch at time T3 as the delayed DQS signal. The delay circuit should delay the HIGH DQS signal such that time T3 is at the center of the data eye 10b. 
At the next falling edge of the clock signal at time T4, the DDR SDRAM asserts a LOW DQS signal and generates data output 20a. At time T5, the data output 20a reaches the data latch as data output 20b. The LOW DQS signal, after propagating through the delay circuit, reaches the data latch at time T6 as the delayed DQS signal. The delay circuit should delay the LOW DQS signal such that time T6 is at the center of the data eye 20b. This sequence is repeated over time.
Designing a delay circuit capable of producing the desired delayed DQS signal is problematic. Fabrication process variations can make identical delay circuits to act differently on different chips and on different wafers. Differences in operating temperatures and operating voltages can cause identical delay circuits to yield different delays to the DQS signal. Moreover, differences in card wiring schemes can have different relative propagation paths for data and the respective DQS signal from the DDR SDRAM to the data latch. As a result, identical delay circuits in different card wiring schemes may cause the asserted DQS signal to reach the data latch at different locations with respect to the center of the respective data eye on a timing diagram.
Accordingly, there is a need for an apparatus and method in which a delay circuit will cause the asserted DQS signal to reach a data latch at a predetermined location with respect to the center of the respective data eye, even if the delay circuit is used in different operating temperatures, different operating voltages, and different card wiring schemes.